Tutorials and Workshops

Saturday (September 17)

• W1: Workshop on Operating System Interference in High Performance Applications (OSIHPA)
  Organizers: Ronald Mraz, IBM T.J. Watson / Matthew Sottile, LANL / Fabrizio Petrini, LANL
• T1: Tutorial on Network Processor Architecture and Compilation (description)
  Organizer: Luddy Harrison, University of Illinois

Afternoon:

• W2: Workshop on Memory Performance: Dealing with Applications, Systems, and Architecture (MEDEA)
  Organizers: Sandro Bartolini, Pierfrancesco Foglia, Roberto Giorgi, and Antonio Prete, University of Pisa, Italy
• T2: Tutorial on Multi-threaded Software Development with the Intel(R) Threading Tools (description)
  Organizers: Douglas Armstrong, Zhiqiang Ma, Paul Petersen, and Sanjiv Shah, Intel
• T3: Tutorial on Structured Distributed Parallel Programming (description)
  Organizers: Lei Pan, NASA Jet Propulsion Laboratory

Sunday (September 18)

• T4: Tutorial on A Tour inside the Azul 384-way Java Appliance (Azul Tutorial)
  Organizers: Cliff Click, Azul

Full day:

• W3: Workshop on Binary Instrumentation and Applications (WBIA)
  Organizers: Robert Cohn, Intel / David Kaeli, Northeastern University
• W4: Workshop on Storage Network Architecture and Parallel I/O (SNAPI)
  Organizers: Qing (Ken) Yang, University of Rhode Island / Hong Jiang, University of Nebraska-Lincoln
• T5: Tutorial on the ROSE C/C++ source-to-source translator (ROSE)
  Organizers: Daniel J. Quinlan, Bronis R. de Supinski, Qing Yi, Richard Vuduc, LLNL, Markus Schordan, Vienna University of Technology

Afternoon:

• T6: Tutorial on the CELL Processor Architecture and Compilation Techniques (CELL Tutorial, description)
  Organizers: Kevin O'Brien, Alexandre Eichenberger, Kathryn O'Brien, Peng Wu, Michael Gschwind, IBM
• T7: Tutorial on Program Locality Models and Their Use in Memory Performance Optimization (website)
  Organizers: Steven Carr, MTU, Trishul Chilimbi, Microsoft Research, Chen Ding, University of Rochester, Youfeng Wu, Intel Microprocessor Technology Labs