The Fourteenth International Conference on
Parallel Architectures and Compilation Techniques
Cut-off date for hotel reservation and conference registration Friday, August 26 5PM EST
| Monday, September 19, 2005 | ||
| 9:00-10:00 am | Keynote I | |
|
Multi-core to the masses
(slides)
Justin Rattner, Intel Senior Fellow | ||
| 10:30-12:30 pm | Profiling: Kathryn S. McKinley | |
|
Variational Path Profiling
(slides)
Erez Perelman, Trishul Chilimbi, and Brad Calder | ||
|
Extended Whole Program Paths
(slides)
Sriraman Tallam, Rajiv Gupta, and Xiangyu Zhang | ||
|
Instruction Based Memory Distance Analysis and its Application to
Optimization
(slides)
Changpeng Fang, Steve Carr, Soner Onder, and Zhenlin Wang | ||
|
HPS: Hybrid Profiling Support
(slides)
Hussam Mousa and Chandra Krintz | ||
| 2:00-3:30 pm | CMPs and Consistency: Christos Kozyrakis | |
|
Maximizing CMP Throughput with Mediocre Cores
(slides)
John D. Davis, James Laudon, Kunle Olukotun | ||
|
Characterization of TCC on Chip Multiprocessors
(slides)
Austen McDonald, JaeWoong Chung, Hassan Chafi, Chi Cao Minh, Brian Carlstrom, Lance Hammond, Christos Kozyrakis, and Kunle Olukotun | ||
|
Store-Ordered Streaming of Shared Memory
Thomas Wenisch, Stephen Somogyi, Nikolaos Hardavellas, Jangwoo Kim, Chris Gniady, Anastassia Ailamaki, and Babak Falsafi | ||
| 4:00-5:30 pm | Dynamic Optimization (Track I): Chandra Krintz | Compiler Analysis A (Track II): Steve Carr |
|
An Event-Driven Multithreaded Dynamic Optimization Framework
Weifeng Zhang, Brad Calder, and Dean M. Tullsen |
Automatic selection of compiler options using non-parametric inferential
statistics
(slides)
M. Haneda, P.M.W. Knijnenburg, and H.A.G. Wijshoff |
|
|
Design and Implementation of A Compiler Framework for Helper Threading on
Multi-Core Processors
Yonghong Song, Spiros Kalogeropulos, and Partha Tirumalai |
Data Centric Transformations on Non-Integer Iteration Spaces
(slides)
Swarup Sahoo and Gagan Agrawal |
|
|
Compiler Directed Early Register Release
(slides)
Timothy M. Jones, Michael F.P. O'Boyle, Jaume Abella, Antonio Gonzalez, and Oguz Ergin |
Efficient Techniques for Advanced Data Dependence Analysis
(slides)
Konstantinos Kyriakopoulos and Kleanthis Psarris |
|
| Tuesday, September 20, 2005 | ||
| 9:00-10:00 am | Keynote II | |
|
Parallel Programming and Parallel Abstractions in Fortress
Guy L. Steele Jr, Sun Microsystems Fellow | ||
| 10:30-12:00 pm | Compiling for Novel Architectures: Brad Calder | |
|
Optimizing Compiler for the CELL Processor
Alexandre E. Eichenberger, Kathryn O'Brien, Kevin K. O'Brien, Peng Wu, Tong Chen, Peter H. Oden, Daniel A. Prener, Janice C. Shepherd, Byoungro So, Zehra Sura, Amy Wang, Tao Zhang, Peng Zhao, and Michael Gschwind | ||
|
Exploiting Coarse-Grained Parallelism to Accelerate Protein Motif Finding
with a Network Processor
Ben Wun, Jeremy Buhler, and Patrick Crowley | ||
|
Automatic Tuning Matrix Multiplication Performance on Graphics Hardware
(slides)
Changhao Jiang and Marc Snir | ||
| 1:30-3:00 pm | VLIW & Performance Analysis: Gabby Silberman | |
|
A Distributed Control Path Architecture for VLIW Processors
(slides)
Hongtao Zhong, Kevin Fan, Scott Mahlke, and Mike Schlansker | ||
|
Variable-Based Multi-Module Data Caches for Clustered VLIW Processors
(slides)
Enric Gibert, Jaume Abella, Jesus Sanchez, Xavier Vera, and Antonio Gonzalez | ||
|
Performance Analysis of System Overheads in TCP/IP Workloads
Nathan L. Binkert, Lisa R. Hsu, Ali G. Saidi, Ronald G. Dreslinski, Andrew L. Schultz, and Steven K. Reinhardt | ||
| 3:30-5:00 pm | Microarchitecture (Track I): Steve Reinhardt | Compiler Analysis B (Track II): Zhenlin Wang |
|
Dual-Core Execution: Building a Highly Scalable Single-Thread Instruction
Window
(slides)
Huiyang Zhou |
Communication Optimizations for Fine-grained UPC Applications
(slides)
Wei-Yu Chen, Costin Iancu, and Katherine Yelick |
|
|
A Simple Divide-and-Conquer Approach for Neural-Class Branch Prediction
(slides)
Gabriel H. Loh |
HUNTing the Overlap
(slides)
Costin Iancu, Paul Hargrove, and Parry Husbands |
|
|
Trace Cache Sampling Filter
(slides)
Michael Behar, Avi Mendelson, and Avinoam Kolodny |
Deep Jam: Conversion of Coarse-Grain Parallelism to Instruction-Level and
Vector Parallelism for Irregular Applications
(slides)
Patrick Carribault, Albert Cohen, and William Jalby |
|
| Wednesday, September 21, 2005 | ||
| 9:00-10:00 am | Reliability & Fault Tolerance:Sam Guyer | |
|
Memory State Compressors for Gigascale Checkpoint/Restore
(slides)
Andreas Moshovos and Alexandros Kostopoulos | ||
|
Exploiting Coarse-Grain Verification Parallelism for Power-Efficient Fault
Tolerance
M. Wasiur Rashid, Edwin J. Tan, Michael C. Huang, and David H. Albonesi | ||
| 10:30-12:00 pm | Memory:Josep Torrellas | |
|
Memory Coloring: A Compiler Approach for Scratchpad Memory Management
Lian Li, Lin Gao, and Jingling Xue | ||
|
Multiple Page Size Modeling and Optimization
(slides)
Calin Cascaval, Evelyn Duesterwald, Peter F. Sweeney, and Robert W. Wisniewski | ||
|
Future Execution: A Hardware Prefetching Technique for Chip
Multiprocessors
Ilya Ganusov and Martin Burtscher | ||